• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring of a semiconductor device, and more particularly, to a method for forming a metal wiring of a semiconductor device in which a plug layer formed in a connection hole has a low resistance, which is suitable for simplifying the process and improving the reliability of the wiring. The metal wiring forming method of the semiconductor device of the present invention comprises the steps of forming an insulating film layer on a semiconductor substrate including a lower layer wiring, and forming a connection hole so that the lower layer wiring is partially exposed by selectively removing the insulating film. Forming a plug layer by forming a first conductive material layer on the insulating film including the connection hole, etching back the first conductive material layer so as to remain only in the connection hole, and forming the plug layer in the plug layer. And removing the impurities to form a low-resistance process, and forming an upper layer wiring to form a second conductive material layer on the insulating film layer including the plug layer.
    公开号:KR19980052475A
    申请号:KR1019960071464
    申请日:1996-12-24
    公开日:1998-09-25
    发明作者:전영권
    申请人:문정환；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Metal wiring formation method of semiconductor device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring of a semiconductor device, and more particularly, to a method for forming a metal wiring of a semiconductor device so as to be suitable for simplifying the process and improving the reliability of the wiring by having a low resistance of the plug layer formed in the connection hole.
    In general, aluminum and its alloy thin films have been widely used as wiring materials for semiconductor circuits because of their high electrical conductivity, easy pattern formation by dry etching, good adhesion with silicon oxide films, and relatively low cost.
    However, as the degree of integration of integrated circuits increases, the size of devices decreases and wiring becomes finer and multilayered. Therefore, step coverage is important in a part having a topology or inside a connection hole such as a contact or a via. It became.
    When sputtering is applied by the metal wiring forming method, the thickness of the wiring film is partially formed by the shadow effect in the portion having the above bend, and is more serious in connection holes having an aspect ratio of 1 or more. .
    Therefore, instead of the physical vapor deposition method, a chemical vapor deposition method capable of depositing a wiring film with a uniform thickness was introduced to form a tungsten film by low pressure chemical vapor deposition (LPCVD), thereby improving the step coverage. Since resistivity is more than twice that of the film, application as a wiring film is difficult.
    Therefore, a method of forming a buried layer (Plug) in the connection hole has been developed.
    The buried layer is formed by selectively growing a tungsten film through a substrate exposed in a connection hole by applying selective chemical vapor deposition (Selective CVD).
    As another method for forming an investment layer, a method of forming a barrier metal film or an adhesive layer is formed by depositing a tungsten film on the entire surface and etching back over the deposition thickness.
    However, in the selective growth method, it is not easy to maintain the growth on the insulating film, and in the method of etching back after full deposition, it is necessary to form a reliable barrier layer or adhesive layer in the connection hole having a high aspect ratio.
    To this end, it is important to secure a minimum thickness above which tungsten nucleation can occur at the bottom or sidewall of the connection hole by applying a collimator or CVD method.
    On the other hand, since the depth of the connection hole depends on the degree of planarization of the insulating film, the surface of the connection hole and the surface of the investment layer are not the same, and the surface of the investment layer is substantially lower.
    And aluminum reflow technology, which deposits aluminum by sputtering and heat treatment or sputtering at high temperature, is embedded in the connection hole, which raises the temperature of the substrate to 500 ° C to increase the fluidity of aluminum particles and flows into the connection hole. Use the method.
    In this case, however, Ti or TiN or a laminated film thereof is applied as a lower layer to increase the adhesiveness of aluminum before deposition of aluminum. The step coverage due to these lower layers may be poor and the surface state may be poor.
    This causes a void in the connection hole or disconnection on the side of the connection hole.
    As another method of forming a metal wiring, a low-resistance conductive film may be deposited using a CVD process to improve step coverage in the connection hole.
    That is, using low resistance materials, such as Cu, Ag, including aluminum, uses DMAH or a DMEAA source in the case of aluminum, and uses a source, such as (hafc) Cu (TMVS), in case of Cu.
    However, in the above metal wiring forming method, since the surface roughness of the CVD thin film is generally large, when processing into a conductive line having a thin line width of 0.5 μm or less, it is very disadvantageous in terms of reflectance of the conductive line, and reliability such as electromigration is difficult. Degrades.
    Hereinafter, a metal wiring of a semiconductor device of the related art will be described with reference to the accompanying drawings.
    1A to 1D are process cross-sectional views of metal wirings of a semiconductor device of the prior art, and FIGS. 2A and 2B are process cross-sectional views of other metal wirings of a semiconductor device of the prior art.
    FIG. 1 illustrates a process of forming a top layer wiring after forming a tungsten plug for connecting a lower wiring and an upper wiring. First, as shown in FIG. 1A, a lower insulating film 2 is formed on a semiconductor substrate 1. Then, the lower wiring 3 is formed on the lower insulating film 2.
    Subsequently, an upper insulating film 4 is formed on the entire surface including the lower wiring 3, and the upper insulating film 4 is etched to selectively expose the lower wiring 3 to form a connection hole 5. .
    As shown in FIG. 1B, the barrier layer 6 is formed on the entire surface including the exposed surface of the lower layer wiring 3 and the side surface of the connection hole 5.
    Subsequently, a first conductive material layer 7 is formed on the barrier layer 6.
    As shown in FIG. 1C, the first conductive material layer 7 and the barrier layer 6 are etched back to form a plug layer 8 in the connection hole 5.
    As shown in FIG. 1D, a second conductive material layer 9 is formed and patterned on the entire surface including the connection hole 5 in which the plug layer 8 is formed to form the wiring.
    At this time, the etch back process of the first conductive material layer 7 for forming the plug layer 8 is over-etched to completely remove the remaining materials in the region where the step occurs.
    In addition, in FIG. 2, in order to lower the resistivity of the plug layer, an upper layer wiring is formed without forming a plug layer, and at the same time, the connection hole is buried.
    First, as shown in FIG. 2A, the lower insulating film 2 is formed on the semiconductor substrate 1, and the lower wiring 3 is formed on the lower insulating film 2.
    Subsequently, the upper insulating film 4 is formed on the entire surface including the lower wiring 3, and the upper insulating film 4 is etched to selectively expose the lower wiring 3 to form the connection hole 5.
    As shown in FIG. 2B, the barrier layer 6 is formed on the entire surface including the surface of the exposed lower layer wiring 3 and the side surface of the connection hole 5.
    Subsequently, an upper layer wiring is formed by depositing and patterning the conductive material layer 7 so that the connection hole 5 is embedded on the barrier layer 6.
    This can simplify the process because the upper layer wiring is formed by filling the connection hole in the CVD process without forming a separate plug layer.
    In the process of forming the metal wiring of the semiconductor element of the prior art, there are the following problems.
    First, in the conventional metal wiring forming process of forming a plug layer by applying an ion etch back process to tungsten selective deposition or blanket deposition in order to improve the step coverage of the conductive material layer in the connection hole portion. The following problems exist.
    First, the resistivity of the plug layer is higher than 5μΩ / cm and a glue layer such as Ti, TiN, TiW, etc. should be formed for full nucleation.
    Second, in order to form the pressure-sensitive adhesive layer as described above, a collimator or a CVD process is required because a minimum thickness of tungsten nucleation must be secured on the bottom or side of the connection hole.
    As shown in FIG. 2, in order to reduce the specific resistance in the connection hole, when the connection hole is buried at the same time as the formation of the upper layer wiring, the connection hole is simultaneously buried and the conductive wire is formed by the CVD process. It lowers the reliability of the wiring.
    The present invention has been made to solve the above-described metal wire wiring problem of the prior art, the metal of the semiconductor device to simplify the process and improve the reliability of the wiring by having a low resistance of the plug layer formed in the connection hole It is an object of the present invention to provide a wiring forming method.
    1A to 1D are cross-sectional views of a metal wiring of a semiconductor device of the prior art.
    2A and 2B are cross-sectional views of another metal wiring of a semiconductor device of the prior art.
    3A to 3E are cross-sectional views of a metal wiring of a semiconductor device of the present invention.
    * Description of the symbols for the main parts of the drawings *
    30 semiconductor substrate 31 lower insulating film
    32: lower layer wiring 33: upper insulating film
    34 connection hole 35a first conductive material layer
    35b: plug layer 35c: low resistance plug layer
    36: second conductive material layer
    In the method of forming a metal wiring of the semiconductor device of the present invention in which the plug layer formed in the connection hole has a low resistance, the process is simplified and the reliability of the wiring is improved, a step of forming an insulating film layer on a semiconductor substrate including a lower wiring and the like And selectively removing the insulating film to form connection holes to partially expose the lower layer wirings, forming a first conductive material layer on the insulating film including the connection holes, and forming the first conductive material layer. Forming a plug layer by etching back so as to remain only in the connection hole, removing the impurities contained in the plug layer, and performing a low resistance process; forming a second conductive material layer on the insulating film layer including the plug layer It is characterized by including the process of forming an upper layer wiring.
    Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the metal wiring forming method of the semiconductor device of the present invention.
    3A to 3F are cross-sectional views of metal wirings of the semiconductor device of the present invention.
    The present invention is to improve the step coverage in the process of forming a plug layer of a conductive material in the connection hole having a high aspect ratio and to simplify the process to lower the specific resistance of the plug.
    First, as shown in FIG. 3A, the lower insulating film 31 is formed on the semiconductor substrate 30 on which the element region and the like are formed, and the lower wiring 32 is formed on the upper side thereof.
    Subsequently, the upper insulating layer 33 is formed on the entire surface including the lower layer wiring 32, and the connection layer 34 is formed by etching the lower layer wiring 32 to be selectively exposed.
    3B, the first conductive material layer 35a is formed on the entire surface including the lower wiring 32 exposed through the connection hole 34 using plasma.
    At this time, the plasma voltage may be 5 to 15W, and the plasma may be a plasma of a carrier gas or a plasma of a source gas.
    In this case, when Al is used as the first conductive material layer 35a, an organometallic compound source such as DMAH or DMEAA is applied to the CVD process by using a MOCVD apparatus to form the upper insulating film 33 and the connection hole 34. An Al film is formed on the side surfaces and the exposed lower wiring lines 32.
    Preferably, dimethylethylamine alane (DMEAA), that is, [(CH 3 ) 2 (CH 3 CH 2 ) N] AlH 3 is incorporated into the MOCVD apparatus using a hydrogen carrier gas by a bubbler, and the pressure is 0.5 to 5 torr, and the flow rate is It forms so that it may be 100-1000 sccm, and temperature may be 130-170 degreeC.
    When Cu is used as a material layer for forming the first conductive material layer 35a, a liquid source such as (hfac) Cu (TMVS) (hexafluroacetylacetonate cutrimethylvinylsilane) or a solid source such as Cu (hfac) 2 may be used as the source gas. To form by MOCVD.
    At this time, vapor deposition temperature is 100 degreeC-200 degreeC, and the thickness is formed in 1000 Pa-2000 Pa.
    Subsequently, as shown in FIG. 3C, the first conductive material layer 35a is etched back to form a plug layer 35b that substantially fills the connection hole 34.
    In this case, in the case of aluminum, which is the main component of the first conductivity type material layer 35a, the plasma is etched back using an anisotropic dry etching process using plasma of a gas containing Cl 2 or the like.
    In order to prevent recesses occurring in the plug layer 35b, a chemical mechanical polishing (CMP) process may be applied.
    In this case, in the case of applying the CMP process, a slurry including an abrasive such as silica and additives such as HNO 3 and HOCl is used.
    Then, as shown in Figure 3c, in order to further reduce the specific resistance of the plug layer (35b) to remove the carbon as a major impurity, that is, at a temperature of 300 ~ 500 ℃ using a hydrogen, oxygen or a mixed gas thereof Heat treatment or plasma treatment.
    The plasma treatment is performed by mixing H 4 O 2 as a source gas into a MOCVD apparatus using a hydrogen carrier gas, under a pressure of 0.5 to 5 torr, a flow rate of 100 to 1000 sccm, and a temperature of 130 to 170 ° C.
    In the low resistance treatment process as described above, the resistivity of the plug layer 35b is reduced to 4 μΩ / cm or less.
    The low resistance treatment step of the plug layer 35b may be performed after the formation of the first conductive material layer 35a before the plug layer 35b is formed.
    Subsequently, as shown in FIG. 3E, the second conductive material layer 36a is formed by physical deposition having excellent surface flatness, such as sputtering, on the entire surface including the plug layer 35b after the low resistance treatment process as described above. To form.
    The second conductive material layer 36a is formed to have a thickness of 3000 to 5000 kPa using a metal material composed mainly of aluminum, Cu, and Ag.
    The second conductive material layer 36a is patterned to form upper wiring.
    In the process of forming the metal wiring of the semiconductor device of the present invention as described above, if the main components constituting the first conductive material layer 35a and the second conductive material layer 36a are different from each other and the reactivity between the two materials is high, the two materials A barrier layer is further formed to suppress the reaction between the layers in order to suppress the reaction between the layers.
    The barrier material may be formed to have a thickness of 300 to 500 Pa by physical vapor deposition such as sputtering of a conductive material having a high melting point such as Ti or TiN, a Ti / TiN laminated film, WN, Ta, or the like.
    In the wiring, when the first conductive material layer 35a is made of aluminum and the second conductive material layer 36a is formed of a material having high reactivity with aluminum such as Cu, the barrier layer is formed as described above. By configuring it, the reaction between the two material layers can be effectively prevented.
    In addition, when the barrier layer is formed to a thin thickness of 200 μs or less, a subsequent amount of thermal control is performed so that the atoms of Cu used as the second conductive material layer 36a are appropriately doped into the aluminum film used as the second conductive material layer 35a. Will be.
    In this way, the aluminum film may be changed to an alloy film containing Cu ions, thereby improving the EM characteristics of the aluminum film, which is a lower conductive layer, and reducing the reaction amount with the semiconductor substrate.
    The metal wiring forming method of the semiconductor element of the present invention improves the step in the connection hole by forming a wiring composed of a buried layer of the first conductivity and a conductive line of the second conductivity, and has the following effects.
    First, since the plug layer may be directly formed on the insulating layer including the connection hole by using a CVD process by using a plasma having no selectivity in forming the plug layer filling the connection hole, the adhesive layer (Glue) for full nucleation is formed. There is no need to form a layer, which simplifies the process.
    Second, impurities contained in the plug layer are removed through heat treatment or plasma treatment to reduce the resistivity of the plug layer, thereby improving the characteristics of the metal wiring.
    Since the conductive line used as the main wiring is formed by physical vapor deposition, the surface roughness of the conductive line is good. Therefore, the flatness of the metal wiring can be improved.
    权利要求:
    Claims (18)
    [1" claim-type="Currently amended] Forming an insulating film layer on a semiconductor substrate including a lower wiring and the like;
    Selectively removing the insulating film to form a connection hole so that the lower layer wiring is partially exposed;
    Forming a first conductive material layer on the insulating film including the connection hole;
    Etching the first conductive material layer so as to remain only in the connection hole to form a plug layer;
    Removing impurities contained in the plug layer to perform low resistance treatment;
    And forming an upper layer wiring by forming a second conductive material layer on the insulating film layer including the plug layer.
    [2" claim-type="Currently amended] 2. The method of claim 1, wherein the plug layer is formed by leaving the first conductive material layer only in the connection hole by an etch back process.
    [3" claim-type="Currently amended] The method of claim 2, wherein when the main component of the first conductive material layer is aluminum, etching is performed by an anisotropic dry etching process using a plasma of a gas containing Cl 2 or the like. .
    [4" claim-type="Currently amended] The method of claim 1, wherein the plug layer is formed by leaving the first conductive material layer only in the connection hole by a CMP process.
    [5" claim-type="Currently amended] The method of claim 4, wherein the CMP process is performed using a slurry containing an abrasive such as silica and additives such as HNO 3 and HOCl.
    [6" claim-type="Currently amended] The method of claim 1, wherein the first conductive material layer is formed of Al, Ag, Cu, or an alloy thereof.
    [7" claim-type="Currently amended] 7. The method of claim 6, wherein when Al is used as the first conductive material layer, an organometallic compound source such as DMAH or DMEAA is used in a CVD process using a MOCVD apparatus.
    [8" claim-type="Currently amended] 8. When using DMEAA as an organometallic compound source, the DMEAA is mixed into the MOCVD apparatus using a hydrogen carrier gas by a bubbler, the pressure is 0.5 to 5 torr, the flow rate is 100 to 1000 sccm, and the temperature is 130 to 170 ° C. The metal wiring formation method of the semiconductor element characterized by forming so that it may become.
    [9" claim-type="Currently amended] The method of claim 6, wherein when Cu is used as the first conductive material layer, MOCVD is performed using a liquid source such as (hfac) Cu (TMVS) or a solid source such as Cu (hfac) 2 as a source gas. A metal wiring forming method of a semiconductor device.
    [10" claim-type="Currently amended] 10. The method for forming a metal wiring of a semiconductor device according to claim 9, wherein the deposition temperature of Cu using the MOCVD apparatus is set at 100 占 폚 to 200 占 폚 and the thickness thereof is set at 1000 占 폚 to 2000 占 폚.
    [11" claim-type="Currently amended] 2. The metal wiring of the semiconductor device according to claim 1, wherein the low resistance treatment step of the plug layer is performed by heat treatment or plasma treatment at a temperature of 300 to 500 DEG C using hydrogen, oxygen, or a mixed gas thereof. Forming method.
    [12" claim-type="Currently amended] 12. The plasma treatment is carried out under conditions of H 4 O 2 as a source gas and mixed into a MOCVD apparatus using a hydrogen carrier gas, a pressure of 0.5 to 5 torr, a flow rate of 100 to 1000 sccm, and a temperature of 130 to 170 ° C. A metal wiring forming method of a semiconductor device, characterized in that.
    [13" claim-type="Currently amended] The method of claim 1, wherein the low resistance treatment step of the plug layer is performed after the formation of the first conductive material layer is completed before forming the plug layer.
    [14" claim-type="Currently amended] The method of claim 1, wherein the second conductive material layer is formed by physical vapor deposition such as sputtering or the like.
    [15" claim-type="Currently amended] 2. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the second conductive material layer is formed to have a thickness of 3000 to 5000 kPa using a metal material composed mainly of aluminum, Cu, and Ag.
    [16" claim-type="Currently amended] 2. The method of claim 1, further comprising forming a barrier layer between the plug layer and the second conductive material layer to suppress a reaction of the two material layers.
    [17" claim-type="Currently amended] The barrier layer is formed using a conductive material having a high melting point, such as Ti or TiN, Ti / TiN laminated film, WN, Ta, or the like to form a thickness of 300 to 500 kPa by physical vapor deposition such as sputtering. A metal wiring forming method of a semiconductor device.
    [18" claim-type="Currently amended] 17. The thermal process of claim 16, wherein the plug layer is formed of aluminum and the second conductive material layer is formed of a material having a high reactivity with aluminum such as Cu. And doping an appropriate amount of atoms of Cu into the second conductive material layer.
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    同族专利:
    公开号 | 公开日
    US6043149A|2000-03-28|
    DE19752637B4|2005-12-29|
    DE19752637A1|1998-07-02|
    JPH10189734A|1998-07-21|
    JP3957380B2|2007-08-15|
    KR100226742B1|1999-10-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-24|Application filed by 문정환, 엘지반도체 주식회사
    1996-12-24|Priority to KR1019960071464A
    1998-09-25|Publication of KR19980052475A
    1999-10-15|Application granted
    1999-10-15|Publication of KR100226742B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960071464A|KR100226742B1|1996-12-24|1996-12-24|Method for forming metal interconnection layer of semiconductor device|
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